Mail Us at : sales@kitomaindonesia.com | Call Us 021 2851 8059

CPU Module PLC Micrex-SX SPH Series

 

 

Kitoma Indonesia - CPU Module PLC Micrex-SX SPH Series

 

CPU Module Micrex-SX SPH series

  • SPH200
  • SPH300
  • SPH300EX
  • SPH2000
  • SPH3000

 

Features
 

Ultra high-speed processing
The CPU module carries out the ultra high-speed processing in basic instructions as follows: SPH300 in 20ns, SPH200 in 70ns, SPH2000 in 30ns, and SPH3000 in 9ns.
 

Muiti-CPU configuration (SPH300/SPH2000/SPH3000)
Up to 8 CPUs can be configured while realizing the high-speed control by load distribution.
 

Redundancy (SPH300/SPH2000)
The 1 to 1 hot standby and the N to 1 cold standby improve the system safety and reliability. (The N to 1 cold standby is provided only to SPH300.)
 

IEC 61131-3
The series is fully compliant with the international standard language IEC 61131-3, which enables you to prepare the programming valid worldwide.
 

Compatible with USB and user ROM
The SPH300, SPH2000 and SPH3000 are provided as the USB and the user ROM versions in the separate format. (NP1PS-32R/74R/117R/245R, NP1PM-48R/48E/256E/256H and NP1PU-048E/256E)
 

Large-capacity battery (optional)
It is possible to extend the memory backup time to three and a half years (at 25°C) by adding an optional large-capacity battery to the SPH300 (74K/117K/245K steps).

 

SPH200

  • NP1PH-08
  • NP1PH-16


SPH300EX

  • NP1PS-74D


SPH300

  • NP1PS-32
  • NP1PS-32R
  • NP1PS-74R
  • NP1PS-117R
  • NP1PS-245R


SPH2000

  • NP1PM-48R
  • NP1PM-48E
  • NP1PM-256E
  • NP1PM-256H


SPH3000MG

  • NP1PU1-256NE


SPH3000MM

  • NP1PU2-048E
  • NP1PU2-256E


SPH3000

  • NP1PU-048E
  • NP1PU-128E
  • NP1PU-256E

 

Performance Specifications

 

  SPH200 SPH300
Type NP1PH-08 NP1PH-16 NP1PS-32 NP1PS-32R NP1PS-74R NP1PS-117R
Control system Stored program, Cyclic scanning system (default task), periodic task, event task
Input / Output connection method Direct connection I/O (SX bus), remote I/O (DeviceNet, OPCN-1, and other remote I/O links)
I/O control system SX bus: Tact synchronization refresh. Remote I/O link: Refresh at 10-ms fixed intervals (not synchronized with scan)
CPU 16-bit OS processor, 16-bit execution processor 32-bit OS processor, 32-bit execution processor
Programming language IL language (Instruction List), ST language (Structured Text), LD language (Ladder Diagram),
FBD language (Function Block Diagram), SFC elements (Sequential Function Chart) To IEC 61131-3
Instruction execution speed Sequence instruction 70ns or more/instruction 20ns or more/instruction
Applied instruction 140ns or more/instruction 40ns or more/instruction
Program memory capacity 8192 steps 16384 steps 32768 steps 75776 steps 119808 steps
Program steps in a POU 4096 steps 8192 steps
Memory
*1
I/O memory (I/Q) 512 words (Max. 8192 points) 512 words (Max. 8192 points)
General memory (M) 4096 words 8192 words 8192 words 32768 words 131072 words
Retain memory (M) 2048 words 4096 words 4096 words 16384 words 32768 words
Instance memory for User FB (M) 2048 words 4096 words 4096 words 16384 words 32768 words
Instance memory for system FB
(M)
  4096 words 8192 words 16384 words 65536 words  
Timer 128 points 256 points 512 points 2048 points
Integrating timer 32 points 64 points 128 points 512 points
Counter 64 points 128 points 256 points 1024 points
Edge detection 256 points 512 points 1024 points 4096 points
    Others 2048 words 4096 words 8192 words 32768 words
System memory (M) 512 words 512 words
Temporary area 4096 words 8192 words
Available basic data type * 2 BOOL,INT,DINT,UINT,UDINT,REAL,TIME,DATE,TOD,DT,STRING,WORD,DWORD
No. of tasks Default tasks (Cyclic scanning): 1, Periodic tasks: 4,
Event tasks: 4 (Total of 4 tasks when Periodic task is used)
No. of POUs in program 2000 (including POUs in the library)
Interface
*3
User ROM card (CF/SD) ROM for SPH200 ROM for SPH200 - O CF card O CF CARD O CF card
USB *4 - - - O O O
Ethernet *5 - - - - - -
Diagnostic function Self-diagnosis (memory check, ROM sum check), System configuration supervising, Module fault monitoring
Security function Set limits to download/upload of the projects, reference, and clear etc,. by the password.
Calendar
Up to 31 Dec. 2069 23:59:59 27sec/month
(when active)
Up to 31 Dec. 2069 23:59:59 27sec/month (when active)
When multi-CPU system is used, time is synchronized.
Battery backup * 7 Backup range: Application programs, system definitions, ZIP files, data memory, calendar IC memory
Battery used: Lithium primary battery
Backup time (at 25˚C): 5 years
Replacement time (at 25˚C): Within 5 minutes
Backup range: Data memory, calendar IC memory
Battery used: Lithium primary battery
Backup time (at 25˚C)
NP1PS-32/32R: 5 years,
NP1PS-74R/117R: Approx. 1.3 years
Replacement time (at 25˚C): within 5 minutes
Memory backup by flash ROM
(contained in CPU module)
Application programs, system definitions, and ZIP files can be saved in the user ROM card. Application programs, system definitions, and ZIP files can be saved in the flash memory built in the CPU.
Memory backup by user ROM card (optional) Application programs, system definitions, and ZIP files can be saved in the user ROM card. Application programs, system definitions, zip files, compressed projects and User's data can be saved in user ROM card (compact flash card).
Internal current consumption 24V DC 85mA or less 24V DC 200mA or less
Mass Approx. 170g Approx. 200g (NP1PS-32/NP1PS-74)
Approx. 220g (NP1PS-32R/NP1PS-74R)
Approx. 220g

 

  SPH300 SPH300EX SPH2000 SPH3000
Type NP1PS- 245R NP1PS- 74D NP1PM- 48R NP1PM- 48E NP1PM- 256E NP1PM- 256H NP1PU- 048E NP1PU- 256E
Control system Stored program, Cyclic scanning system (default task), periodic task, event task
Input / Output connection method Direct connection I/O (SX bus), remote I/O (DeviceNet, OPCN-1, and other remote I/O links)
I/O control system SX bus: Tact synchronization refresh.
Remote I/O link: Refresh at 10-ms fixed intervals (not synchronized with scan)
CPU 32-bit OS processor, 32-bit execution processor 32-bit OS processor
Programming language IL language (Instruction List), ST language (Structured Text), LD language (Ladder Diagram), FBD language (Function Block Diagram), SFC elements (Sequential Function Chart) To IEC 61131-3
Instruction execution speed Sequence instruction 20ns or more/instruction 30ns or more/instruction 9ns or more/instruction
Applied instruction 40ns or more/instruction 40ns or more/instruction 8ns or more/instruction
Program memory capacity 250880 steps 75776 steps x 2 49152 steps 262144 steps 49152 steps 262144 steps
Program steps in a POU 8192 steps 16384 steps
Memory
*1
I/O memory (I/Q) 512 words (Max. 8192 points) 512 words x 2
(Max. 8192 points x 2)
512 words (Max. 8192 points)
General memory (M) 262144 words 32768 words x 2 65536 words 1703936 words 98034 words 1703936 words
Retain memory (M) 130048 words 8192 words x 2 8192 words 262144 words 40960 words 237568 words
Instance memory for User FB (M) 66560 words 16384 words x 2 8192 words 65536 words 40960 words 73728 words
Instance memory for system FB
(M)
  65536 words